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  november 2009 doc id 16782 rev 1 1/27 1 VN750PS-E high side driver features ecopack ? : lead free and rohs compliant automotive grade: compliance with aec guidelines cmos compatible input on-state open-load detection off-state open-load detection shorted load protection undervoltage and overvoltage shutdown protection against loss of ground very low standby current reverse battery protection (see figure 24 ) description the VN750PS-E is a monolithic device designed in stmicroelectronics vipower m0-3 technology intended for driving any kind of load with one side connected to ground. active v cc pin voltage clamp protects the device against low energy spikes (see iso7637 transient compatibility table). acti ve current limitation combined with thermal shutdown and automatic restart help protect the device against overload. the device detects open load condition in on and off-state. output shorted to v cc is detected in the off-state. device automatically turns off in case of ground pin disconnection. type r ds(on) i out v cc VN750PS-E 60 m 6a 36v table 1. device summary package order codes tube tape and reel so-8 VN750PS-E vn750pstr-e so-8 www.st.com
contents VN750PS-E 2/27 doc id 16782 rev 1 contents 1 block diagram and pin description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5 2 electrical specifications . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6 2.1 absolute maximum ratings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6 2.2 thermal data . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7 2.3 electrical characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7 2.4 electrical characteristics curves . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13 2.5 gnd protection network against reverse battery . . . . . . . . . . . . . . . . . . . 16 2.6 load dump protection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17 2.7 microcontroller i/os protection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17 2.8 open-load detection in off-state . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17 2.9 so-8 maximum demagnetization energy (v cc = 13.5 v) . . . . . . . . . . . . . 19 3 package and pcb thermal data . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20 3.1 so-8 thermal data . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20 4 package and packing information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23 4.1 so-8 package information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23 4.2 so-8 packing information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25 5 revision history . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26
VN750PS-E list of tables doc id 16782 rev 1 3/27 list of tables table 1. device summary . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1 table 2. suggested connections for unused and not connected pins . . . . . . . . . . . . . . . . . . . . . . . . 5 table 3. absolute maximum ratings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6 table 4. thermal data. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7 table 5. electrical characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7 table 6. truth table. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10 table 7. electrical transient requirements on v cc pin (part 1/3). . . . . . . . . . . . . . . . . . . . . . . . . . . . 10 table 8. electrical transient requirements on v cc pin (part 2/3). . . . . . . . . . . . . . . . . . . . . . . . . . . . 11 table 9. electrical transient requirements on v cc pin (part 3/3). . . . . . . . . . . . . . . . . . . . . . . . . . . . 11 table 10. thermal parameter . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22 table 11. so-8 mechanical data . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23 table 12. document revision history . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26
list of figures VN750PS-E 4/27 doc id 16782 rev 1 list of figures figure 1. block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5 figure 2. configuration diagram (top view) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5 figure 3. current and voltage conventions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6 figure 4. status timings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9 figure 5. switching time waveforms . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10 figure 6. waveforms . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12 figure 7. off-state output current . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13 figure 8. high level input current . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13 figure 9. input clamp voltage. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13 figure 10. status leakage current . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13 figure 11. status low output voltage . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13 figure 12. status clamp voltage . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13 figure 13. on-state resistance vs t case . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14 figure 14. on-state resistance vs v cc . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14 figure 15. open-load on-state detection threshold . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14 figure 16. input high level . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14 figure 17. input low level . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14 figure 18. input hysteresis voltage . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14 figure 19. overvoltage shutdown . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15 figure 20. open-load off-state voltage detection threshold . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15 figure 21. turn-on voltage slope (part 1/2) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15 figure 22. turn-off voltage slope (part 1/2) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15 figure 23. i lim vs t case . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15 figure 24. application schematic . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16 figure 25. open-load detection in off-state . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18 figure 26. so-8 maximum turn-off current versus inductance . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19 figure 27. pc board. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20 figure 28. rthj-amb vs pcb copper area in open box free air condition . . . . . . . . . . . . . . . . . . . . . . . 20 figure 29. so-8 thermal impedance junction ambient single pulse . . . . . . . . . . . . . . . . . . . . . . . . . . 21 figure 30. thermal fitting model of a single channel . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21 figure 31. so-8 package dimensions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23 figure 32. so-8 tube shipment (no suffix) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25 figure 33. so-8 tape and reel shipment (suffix ?tr?) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2 5
VN750PS-E block diagram and pin description doc id 16782 rev 1 5/27 1 block diagram and pin description figure 1. block diagram figure 2. configurati on diagram (top view) table 2. suggested connections for unused and not connected pins connection/pin status n.c. output input floating x x x x to ground x through 10 k resistor undervoltage over temperature v cc gnd input output overvoltage current limiter logic driver power clamp status v cc clamp on - state open-load off-state open-load and output shorted to v cc detection detection detection detection detection so-8 v cc v cc output output n.c. gnd status input 1 4 5 8
electrical specifications VN750PS-E 6/27 doc id 16782 rev 1 2 electrical specifications figure 3. current and voltage conventions 2.1 absolute maximum ratings stress values that exceed those listed in t he ?absolute maximum ratings? table can cause permanent damage to the device. these are stress ratings only and operation of the device at these or any other conditions greater than those indicated in the operating sections of this specification is not implied. exposure to absolute maximum rating conditions for extended periods may affect device reliability. refer also to the stmicroelectronics sure program and other relevant quality documents. input i s i in v in v cc status i stat v stat gnd v cc i out v out i gnd output v f table 3. absolute maximum ratings symbol parameter value unit v cc dc supply voltage 41 v - v cc reverse dc supply voltage - 0.3 v - i gnd dc reverse ground pin current - 200 ma i out dc output current internally limited a - i out reverse dc output current - 6 a i in dc input current +/-10 ma i stat dc status current +/- 10 ma v esd electrostatic discharge (human body model: r=1.5 k ; c=100 pf) - input - status - output - v cc 4000 4000 5000 5000 v v v v
VN750PS-E electrical specifications doc id 16782 rev 1 7/27 2.2 thermal data 2.3 electrical characteristics values specified in this section are for 8 v 8 v i out =2 a; v cc >8 v 60 120 m m
electrical specifications VN750PS-E 8/27 doc id 16782 rev 1 i s supply current off-state; v cc =13 v; v in =v out =0 v off-state; v cc =13 v; v in =v out =0 v; t j =25 c on-state; v cc =13 v; v in =5 v; i out =0 a 10 10 2 25 20 3.5 a a ma i l(off1) off-state output current v in =v out =0 v 0 50 a i l(off2) off-state output current v in =0 v; v out =3.5 v -75 0 a i l(off3) off-state output current v in =v out =0 v; vcc=13 v; t j =125 c 5a i l(off4) off-state output current v in =v out =0 v; vcc=13 v; t j =25 c 3a switching (v cc =13v) t d(on) turn-on delay time r l =6.5 from v in rising edge to v out =1.3 v 40 s t d(off) turn-off delay time r l =6.5 from v in falling edge to v out =11.7 v 30 s dv out /dt (on) turn-on voltage slope r l =6.5 from v out =1.3 v to v out =10.4 v see figure 21. v/s dv out /dt (off) turn-off voltage slope r l =6.5 from v out =11.7 v to v out =1.3 v see figure 22. v/s input pin v il input low level 1.25 v i il low level input current v in =1.25 v 1 a v ih input high level 3.25 v i ih high level input current v in =3.25 v 10 a v hyst input hysteresis voltage 0.5 v v icl input clamp voltage i in =1 ma i in =-1 ma 6 6.8 -0.7 8v v v cc output diode v f forward on voltage -i out =1.3 a; t j =150 c 0.6 v status pin v stat status low output voltage i stat =1.6 ma 0.5 v i lstat status leakage current normal operation; v stat =5 v 10 a c stat status pin input capacitance normal operation; v stat =5 v 100 pf v scl status clamp voltage i stat =1 ma i stat =-1 ma 66.8 -0.7 8v v table 5. electrical characteristics (continued) symbol parameter test conditions min. typ. max. unit
VN750PS-E electrical specifications doc id 16782 rev 1 9/27 figure 4. status timings protections (1) t tsd shutdown temperature 150 175 200 c t r reset temperature 135 c t hyst thermal hysteresis 7 15 c t sdl status delay in overload condition t j >t jsh 20 ms i lim current limitation 9v v ol t dol(on) t j > t jsh v in v stat t sdl t sdl
electrical specifications VN750PS-E 10/27 doc id 16782 rev 1 figure 5. switching time waveforms table 6. truth table conditions input output status normal operation l h l h h h current limitation l h h l x x h (t j < t tsd ) h (t j > t tsd ) l over temperature l h l l h l undervoltage l h l l x x overvoltage l h l l h h output voltage > v ol l h h h l h output current < i ol l h l h h l table 7. electrical transient requirements on v cc pin (part 1/3) iso t/r 7637/1 test pulse test levels i ii iii iv delays and impedance 1 -25 v -50 v -75 v -100 v 2 ms 10 2 +25 v +50 v +75 v +100 v 0.2 ms 10 t t v out v in 80% 10% dv out /dt (on) t d(off) 90% dv out /dt (off) t d(on)
VN750PS-E electrical specifications doc id 16782 rev 1 11/27 3a -25 v -50 v -100 v -150 v 0.1 s 50 3b +25 v +50 v +75 v +100 v 0.1 s 50 4 -4 v -5 v -6 v -7 v 100 ms, 0.01 5 +26.5 v +46.5 v +66.5 v +86.5 v 400 ms, 2 table 8. electrical transient requirements on v cc pin (part 2/3) iso t/r 7637/1 test pulse test levels results i ii iii iv 1cccc 2cccc 3acccc 3bcccc 4cccc 5c e e e table 9. electrical transient requirements on v cc pin (part 3/3) class contents c all functions of the device are performed as designed after exposure to disturbance. e one or more functions of the device is not performed as designed after exposure to disturbance and cannot be returned to prope r operation without replacing the device. table 7. electrical transient requirements on v cc pin (part 1/3) (continued) iso t/r 7637/1 test pulse test levels i ii iii iv delays and impedance
electrical specifications VN750PS-E 12/27 doc id 16782 rev 1 figure 6. waveforms open load without external pull-up status input normal operation undervoltage v cc v usd v usdhyst input overvoltage v cc v cc >v ov status input status status input status input open load with external pull-up undefined load voltage v cc v ol v ol
VN750PS-E electrical specifications doc id 16782 rev 1 13/27 2.4 electrical char acteristics curves figure 7. off-state output current figure 8. high level input current figure 9. input clamp voltage f igure 10. status leakage current figure 11. status low output voltage figure 12. status clamp voltage -50 -25 0 25 50 75 100 125 150 175 tc (oc) -1 -0.5 0 0.5 1 1.5 2 2.5 3 il(off1) (ua) off state vcc=36v vin=vout=0v -50 -25 0 25 50 75 100 125 150 175 tc (oc) 0 1 2 3 4 5 6 7 iih (ua) vin=3.25v -50 -25 0 25 50 75 100 125 150 175 tc (c) 6 6.2 6.4 6.6 6.8 7 7.2 7.4 7.6 7.8 8 vicl (v) iin=1ma -50 -25 0 25 50 75 100 125 150 175 tc (c) 0 0.01 0.02 0.03 0.04 0.05 ilstat (ua) vstat=5v -50 -25 0 25 50 75 100 125 150 175 tc (oc) 0 0.1 0.2 0.3 0.4 0.5 0.6 vstat (v) istat=1.6ma -50 -25 0 25 50 75 100 125 150 175 tc (c) 6 6.2 6.4 6.6 6.8 7 7.2 7.4 7.6 7.8 8 vscl (v) istat=1ma
electrical specifications VN750PS-E 14/27 doc id 16782 rev 1 figure 13. on-state resistance vs t case figure 14. on-state resistance vs v cc figure 15. open-load on-state detection threshold figure 16. input high level figure 17. input low level figure 18. input hysteresis voltage -50 -25 0 25 50 75 100 125 150 175 tc (oc) 0 20 40 60 80 100 120 140 ron (mohm) iout=2a vcc=8v; 13v; 36v 5 10152025303540 vcc (v) 20 30 40 50 60 70 80 90 100 110 120 ron (mohm) iout=2a tc= - 40c tc= 25c tc= 125c tc= 150c -50 -25 0 25 50 75 100 125 150 175 tc (oc) 0 20 40 60 80 100 120 140 160 180 200 220 iol (ma) vcc=13v vin=5v -50 -25 0 25 50 75 100 125 150 175 tc (oc) 2 2.2 2.4 2.6 2.8 3 3.2 3.4 3.6 vih (v) -50 -25 0 25 50 75 100 125 150 175 tc (oc) 1 1.2 1.4 1.6 1.8 2 2.2 2.4 2.6 2.8 vil (v) -50 -25 0 25 50 75 100 125 150 175 tc (oc) 0.5 0.6 0.7 0.8 0.9 1 1.1 1.2 1.3 1.4 1.5 vhyst (v)
VN750PS-E electrical specifications doc id 16782 rev 1 15/27 figure 19. overvoltage shutdown figure 20. open-load off-state voltage detection threshold figure 21. turn-on voltage slope (part 1/2) figure 22. turn-off voltage slope (part 1/2) figure 23. i lim vs t case -50 -25 0 25 50 75 100 125 150 175 tc (c) 30 32 34 36 38 40 42 44 46 48 50 vov (v) -50 -25 0 25 50 75 100 125 150 175 tc (oc) 1 1.5 2 2.5 3 3.5 4 4.5 5 vol (v) vin=0v -50 -25 0 25 50 75 100 125 150 175 tc (oc) 0 100 200 300 400 500 600 700 800 900 1000 dvout/dt/(on) (v/ms) vcc=13v rl=6.5ohm -50 -25 0 25 50 75 100 125 150 175 tc (oc) 0 50 100 150 200 250 300 350 400 450 500 dvout/dt(off) (v/ms) vcc=13v rl=6.5ohm -50 -25 0 25 50 75 100 125 150 175 tc (oc) 0 2 4 6 8 10 12 14 16 18 20 ilim (a) vcc=13v
electrical specifications VN750PS-E 16/27 doc id 16782 rev 1 figure 24. application schematic 2.5 gnd protection network against reverse battery solution 1: resistor in the ground line (r gnd only). this can be used with any type of load. the following is an indication on how to dimension the r gnd resistor. 1. r gnd 600 mv / (i s(on)max ). 2. r gnd (? v cc ) / (-i gnd ) where -i gnd is the dc reverse ground pin current and can be found in the absolute maximum rating section of the device datasheet. power dissipation in r gnd (when v cc <0: during reverse battery situations) is: p d = (-v cc ) 2 /r gnd this resistor can be shared amongst several different hsds. please note that the value of this resistor should be calculated with formula (1) where i s(on)max becomes the sum of the maximum on-state currents of the different devices. please note that if the microprocessor ground is not shared by the device ground then the r gnd will produce a shift (i s(on)max * r gnd ) in the input thresholds and the status output values. this shift will vary depending on how ma ny devices are on in the case of several high side drivers sharing the same r gnd . if the calculated power dissipation leads to a large resistor or several devices have to share the same resistor then st suggests to utilize solution 2 (see below). solution 2: diode (d gnd ) in the ground line a resistor (r gnd =1 k ) should be inserted in parallel to d gnd if the device drives an inductive load. this small signal diode can be safely shared amongst several different hsds. also in this case, the presence of the grou nd network will produce a shift ( 600mv) in the input threshold and in the status output values if the microprocessor ground is not common to the v cc gnd output d gnd r gnd d ld c +5v r prot v gnd status input +5v r prot
VN750PS-E electrical specifications doc id 16782 rev 1 17/27 device ground. this shift will not vary if more than one hsd shares t he same diode/resistor network. series resistor in input and status lines are also required to prevent that, during battery voltage transient, the current exceeds the absolute maximum rating. safest configuration for unused input and status pin is to leave them unconnected. 2.6 load dump protection d ld is necessary ( voltage transient suppressor ) if the load dump peak voltage exceeds the v cc max dc rating. the same applies if the device is subject to transients on the v cc line that are greater than the ones shown in the iso 7637-2: 2004(e) table. 2.7 microcontroller i/os protection if a ground protection network is used and negative transient are present on the v cc line, the control pins will be pulled negative. st suggests to insert a resistor (r prot ) in line to prevent the c i/os pins to latch-up. the value of these resistors is a compromise between the leakage current of c and the current required by the hsd i/os (input levels compatibilit y) with the latch-up limit of c i/os. -v ccpeak /i latchup r prot (v oh c -v ih -v gnd ) / i ihmax calculation example: for v ccpeak = - 100 v and i latchup 20 ma; v oh c 4.5 v 5k r prot 65 k . recommended values: r prot =10 k . 2.8 open-load detecti on in off-state off-state open-load detection requires an external pull-up resistor (r pu ) connected between output pin and a positive supply voltage (v pu ) like the +5v line used to supply the microprocessor. the external resistor has to be selected according to the following requirements: 1. no false open-load indication when load is connected: in this case we have to avoid v out to be higher than v olmin ; this results in the following condition v out =(v pu /(r l +r pu ))r l electrical specifications VN750PS-E 18/27 doc id 16782 rev 1 figure 25. open-load detection in off-state v ol v batt. v pu r pu r l r driver + logic + - input status v cc out ground i l(off2)
VN750PS-E electrical specifications doc id 16782 rev 1 19/27 2.9 so-8 maximum dema gnetization energy (v cc = 13.5 v) figure 26. so-8 maximum turn-off current versus inductance note: values are generated with r l =0 w .in case of repetitive pulses, t jstart (at beginning of each demagnetization) of every pulse must not exceed the temperature specified above for curves a and b. c: t jstart = 125 c repetitive pulse a: t jstart = 150 c single pulse b: t jstart = 100 c repetitive pulse demagnetization demagnetization demagnetization t v in , i l 1 10 100 0.1 1 10 100 l(mh) i lmax (a) a b c
package and pcb the rmal data VN750PS-E 20/27 doc id 16782 rev 1 3 package and pcb thermal data 3.1 so-8 thermal data figure 27. pc board 1. layout condition of r th and z th measurements (pcb fr4 area = 58 mm x 58 mm, pcb thickness = 2 mm, cu thickness=35 m, copper areas: 0.14 cm 2 , 0.8 cm 2 , 2 cm 2 ). figure 28. r thj-amb vs pcb copper area in open box free air condition 70 75 80 85 90 95 100 105 110 00.511.522.5 pcb cu heatsink area (cm^2) rt hj _am b ( oc/w) so-8 at 2 pins connected to tab
VN750PS-E package and pcb thermal data doc id 16782 rev 1 21/27 figure 29. so-8 thermal impedance junction ambient single pulse equation 1: pulse calculation formula where = t p /t figure 30. thermal fitting model of a single channel 0.01 0.1 1 10 100 1000 0.0001 0.001 0.01 0.1 1 10 100 1000 time (s) zth (c/w) 0.5 cm 2 2 cm 2 z th r th z thtp 1 ? () + ? =
package and pcb the rmal data VN750PS-E 22/27 doc id 16782 rev 1 table 10. thermal parameter area/island (cm 2 )0.52 r1 (c/w) 0.05 r2 (c/w) 0.8 r3 (c/w) 3.5 r4 (c/w) 21 r5 (c/w) 16 r6 (c/w) 58 28 c1 (ws/c) 0.006 c2 (ws/c) 0.0026 c3 (ws/c) 0.0075 c4 (ws/c) 0.045 c5 (ws/c) 0.35 c6 (ws/c) 1.05 2
VN750PS-E package and packing information doc id 16782 rev 1 23/27 4 package and packing information in order to meet environmental requirements, st offers these devices in different grades of ecopack ? packages, depending on their level of environmental compliance. ecopack ? specifications, grade definitions and product status are available at: www.st.com . ecopack ? is an st trademark. 4.1 so-8 package information figure 31. so-8 package dimensions table 11. so-8 mechanical data dim. mm min. typ. max. a 1.75 a1 0.10 0.25 a2 1.25 b 0.28 0.48 c 0.17 0.23 d (1) 4.80 4.90 5.00 0016023 d
package and packing information VN750PS-E 24/27 doc id 16782 rev 1 e 5.80 6.00 6.20 e1 (2) 3.80 3.90 4.00 e 1.27 h 0.25 0.50 l 0.40 1.27 l1 1.04 k 0 8 ccc 0.10 1. dimension ?d? does not include mold fl ash, protrusions or gate burrs. mold flash, protrusions or gate burrs shall not exceed 0.15 mm in total (both side). 2. dimension ?e1? does not include interlead flash or pr otrusions. interlead flash or protrusions shall not exceed 0.25 mm per side. table 11. so-8 mechanical data (continued) dim. mm min. typ. max.
VN750PS-E package and packing information doc id 16782 rev 1 25/27 4.2 so-8 packing information the devices can be packed in tube or tape and reel shipments (see the device summary on page 1 ). figure 32. so-8 tube shipment (no suffix) figure 33. so-8 tape and reel shipment (suffix ?tr?) all dimensions are in mm. base q.ty 100 bulk q.ty 2000 tube length ( 0.5) 532 a 3.2 b 6 c ( 0.1) 0.6 c b a tape dimensions according to electronic industries association (eia) standard 481 rev. a, feb. 1986 all dimensions are in mm. tape width w 12 tape hole spacing p0 ( 0.1) 4 component spacing p 8 hole diameter d (+0.1/-0) 1.5 hole diameter d1 (min) 1.5 hole position f ( 0.05) 5.5 compartment depth k (max) 4.5 hole spacing p1 ( 0.1) 2 top cover tape end start no components no components components 500mm min 500mm min empty components pockets saled with cover tape. user direction of feed reel dimensions all dimensions are in mm. base q.ty 2500 bulk q.ty 2500 a (max) 330 b (min) 1.5 c ( 0.2) 13 f 20.2 g (+ 2 / -0) 12.4 n (min) 60 t (max) 18.4
revision history VN750PS-E 26/27 doc id 16782 rev 1 5 revision history table 12. document revision history date revision changes 23-nov-2009 1 initial release.
VN750PS-E doc id 16782 rev 1 27/27 please read carefully: information in this document is provided solely in connection with st products. stmicroelectronics nv and its subsidiaries (?st ?) reserve the right to make changes, corrections, modifications or improvements, to this document, and the products and services described he rein at any time, without notice. all st products are sold pursuant to st?s terms and conditions of sale. purchasers are solely responsible for the choice, selection and use of the st products and services described herein, and st as sumes no liability whatsoever relating to the choice, selection or use of the st products and services described herein. no license, express or implied, by estoppel or otherwise, to any intellectual property rights is granted under this document. i f any part of this document refers to any third party products or services it shall not be deemed a license grant by st for the use of such third party products or services, or any intellectual property contained therein or considered as a warranty covering the use in any manner whatsoev er of such third party products or services or any intellectual property contained therein. unless otherwise set forth in st?s terms and conditions of sale st disclaims any express or implied warranty with respect to the use and/or sale of st products including without limitation implied warranties of merchantability, fitness for a parti cular purpose (and their equivalents under the laws of any jurisdiction), or infringement of any patent, copyright or other intellectual property right. unless expressly approved in writing by an authorized st representative, st products are not recommended, authorized or warranted for use in military , air craft, space, life saving, or life sustaining applications, nor in products or systems where failure or malfunction may result in personal injury, death, or severe property or environmental damage. st products which are not specified as "automotive grade" may only be used in automotive applications at user?s own risk. resale of st products with provisions different from the statements and/or technical features set forth in this document shall immediately void any warranty granted by st for the st product or service described herein and shall not create or extend in any manner whatsoev er, any liability of st. st and the st logo are trademarks or registered trademarks of st in various countries. information in this document supersedes and replaces all information previously supplied. the st logo is a registered trademark of stmicroelectronics. all other names are the property of their respective owners. ? 2009 stmicroelectronics - all rights reserved stmicroelectronics group of companies australia - belgium - brazil - canada - china - czech republic - finland - france - germany - hong kong - india - israel - ital y - japan - malaysia - malta - morocco - philippines - singapore - spain - sweden - switzerland - united kingdom - united states of america www.st.com


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